In this module we will study automatic test pattern generation (ATPG) using sensitization–propagation -justification approach. We will first introduce the basics of. 1. VLSI Design Verification and Testing. Combinational ATPG Basics. Mohammad Tehranipoor. Electrical and Computer Engineering. University of Connecticut. Boolean level. • Classical ATPG algorithms reach their limits. ➢ There is a need for more efficient ATPG tools! 6. Circuits. • Basic gates. – AND, OR, EXOR, NOT.

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Combinational ATPG Basics

ATPG is a topic that is basicw by several conferences throughout the year. Various search strategies and heuristics have been devised to find a shorter sequence, or to find a sequence faster. Fault propagation moves the resulting signal value, or fault effect, forward by sensitizing a path from the fault site to a primary output.

Bzsics page was last edited on 23 Novemberat By using this site, you agree to the Terms of Use and Privacy Policy. Bbasics effectiveness of ATPG is measured by the number of modeled defects, or fault modelsdetectable and by basicd number of generated patterns. The stuck-at fault model is a logical fault model because no delay information is basicw with the fault definition. The logic values observed at the device’s atph outputs, while applying a test pattern to some device under test DUTare called the output basica that test pattern.

During design validation, engineers can no longer ignore the effects of crosstalk and power supply noise on reliability and performance. Hence, if a circuit has n signal lines, there are potentially 2n stuck-at faults defined on the circuit, of which some can be viewed as being equivalent atpb others.

The classic example of this is a redundant circuit, designed such that no single fault causes the output to change. Second, it is possible that a detection pattern exists, but the algorithm cannot find one. Fault activation establishes a signal value at the fault model site that is opposite of the value produced by the fault model. The single stuck-at fault model is structural because it is basjcs based on a structural gate-level circuit model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit.

Historically, ATPG has focused on a set of faults derived from a gate-level fault model. Views Read Edit View history. In the latter case, dominant driver keeps its value, while the other one gets the AND or OR value of its own and the dominant driver. A fault model is a mathematical description of how a defect alters design behavior. ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test full scansynchronous sequential, or asynchronous sequentialthe level of abstraction used to represent the circuit under test gate, register-transfer, switchand the required test quality.


However, according to reported results, no single strategy or heuristic out-performs others for all applications or circuits.

Automatic test pattern generation

A defect is an error caused in a device during the manufacturing process. Bridging to VDD or Vss is equivalent to stuck at fault model. Even a simple stuck-at fault requires a sequence of vectors for detection in a sequential circuit. This observation implies that a test generator should include a comprehensive set of heuristics.

Retrieved from ” basivs The ATPG process for a targeted fault consists of two phases: Testing very-large-scale integrated circuits with a high fault coverage is a difficult task because of complexity.

Current fault modeling and vector-generation techniques are giving way to new models and techniques that consider timing information during test generation, that are scalable to larger designs, and that can capture extreme design conditions. Sequential-circuit ATPG searches for a sequence of test vectors to detect a particular fault atph the space of all possible test vector sequences.

This allows using a relatively simple vector matrix to quickly test all the comprising FFs, as well as to trace failures to specific FFs.

Any single fault from the set of equivalent faults can represent the whole set. As design trends move toward nanometer technology, new manufacture testing problems are emerging.

Removing equivalent faults from entire set of faults is called fault collapsing. The combinational ATPG method allows testing the individual nodes atpgg flip-flops of the logic circuit without being concerned with the operation of the overall circuit. First, the fault may be intrinsically undetectable, such that no patterns exist that can detect that particular fault.

The generated patterns are used to test semiconductor devices after manufacture, or to assist with determining the cause of failure failure analysis [1]. These metrics generally indicate test quality higher with more fault detections and test application time higher with more patterns. ATPG can fail to find a test for a particular fault in at least two cases.


In stuck-short, a transistor behaves as it is always conducts or stuck-onand stuck-open is when a transistor never conducts current or stuck-off.

NPTEL :: Computer Science and Engineering – VLSI Design Verification and Test

Also, due to the presence of memory elements, the controllability and observability of the internal signals in a sequential circuit are in general much more difficult than those in a combinational logic circuit. If one driver dominates the other driver in a atpf situation, the dominant driver forces the logic to the other one, in such case a dominant bridging fault is used. Equivalent faults produce the same faulty behavior for all input patterns. However, these test generators, combined with low-overhead DFT techniques such as partial scanhave shown a certain degree of success in testing large designs.

For designs that are sensitive basocs area or performance overhead, the solution of using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG.

It is also called a permanent fault model because the faulty effect is assumed to be permanent, in contrast to intermittent faults which occur seemingly at random and transient faults which occur sporadically, perhaps depending on operating conditions e.

During test, a so-called scan-mode is enabled forcing all flip-flops FFs to be connected in a simplified fashion, effectively bypassing their interconnections as intended during normal operation.

The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern. From Wikipedia, the free encyclopedia. This model is used to describe faults for CMOS logic gates. A fault is said to be detected by a test pattern if the output of that test pattern, when testing a device that has only that one fault, is different than the expected output.

At transistor level, a transistor maybe stuck-short or stuck-open. In the past several decades, the most popular fault model used in practice is the single stuck-at fault model. In such a circuit, any single fault will be inherently undetectable.

Therefore, many different ATPG methods have been developed to address combinational and sequential circuits.

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